Scalable Superscalar Processors

by Bradley C. Kuszmaul

When & Where: 12:00 noon, Monday Feb 8, AKW 500

The poor scalability of existing superscalar processors has been of concern in the computer engineering community. In particular, the critical-path lengths of many components in existing implementations grow as N^2, or faster, where N is the fetch width, the issue width, or the window size. Furthermore, it is widely believed that the N^2 bound cannot be improved upon. Some researchers have concluded that high-issue-width processors with fast clocks cannot be built.

In this talk I demonstrate how to implement a fast high-issue-width superscalar processor. I present a processor microarchitecture, called the Ultrascalar processor, that has a critical-path length of O(log(N)) gate delays, O(sqrt(N)) wire delay (speed-of-light delay), and chip area O(N), all of which are optimal bounds. A 64-issue processor core has been designed using the Magic VLSI editor. The Ultrascalar is a beautiful processor!

This talk presents joint work with Dana S. Henry, Vinod Viswanath and Gabe Loh.